HDMI Overview

Tue Dec 13 17:42:53 CST 2022

0_HDMI-Overview-HornmicLink

HDMI Overview

The HDMI architecture consists of a sinks and a sources. A device may have one or more HDMI inputs and outputs.

Components of HDMI

The HDMI cable and connector carry four differential pairs that form the minimum transmission differential signal (TMDS) data and clock channels for HDMI 1.4 and HDMI 2.0. For HDMI 2.1, the HDMI cable and connector carry four fixed rate link (FRL) data channels. You can use these channels to transmit video, audio, and auxiliary data.

The DDC configures and exchanges status between a single source and a single receiver. The source uses the DDC to read the receiver's Enhanced Extended Display Identification Data (E-EDID) to discover the receiver's configuration and functionality.

Optional Consumer Electronics Control (CEC) protocols provide advanced control between the various audiovisual products in your environment.

The optional HDMI Ethernet and Audio Return Channel (HEAC) provides an Ethernet-compatible data network between the connected device and the audio return channel in the opposite direction of the TMDS. HEAC also uses hot plug detection (HPD) lines for link detection.

The figure below illustrates the blocks in the HDMI Intel FPGA IP for TMDS Mode.

1_blocks-in-the-HDMI-FPGA-IP-for-TMDS-Mode

Based on TMDS encoding, the HDMI protocol allows the transmission of audio and video data between the source and the receiving device.

The HDMI interface consists of three color channels and one clock channel. You can use each color line to transmit individual RGB colors and auxiliary data.

TMDS encoding is based on an 8b/10b algorithm. The protocol attempts to minimize data channel transitions while maintaining enough transitions so that the receiver device can reliably lock to the data stream.

Fixed Rate Link (FRL)

2_HDMI-FRL-Mode-Fixed-Rate-Link

Before HDMI 2.1, there are three channels carrying data and one channel carrying the TMDS clock. When operating in FRL mode, the clock channel also carries data. Since the HDMI 2.1 specification requires backward compatibility with HDMI 1.4 and HDMI 2.0, you need to configure the 4th channel to carry data or clock at runtime.

You can configure FRL mode as 3-channel and 4-channel. In 3-channel FRL mode, each channel can run at 3 Gbps or 6 Gbps. In 4-channel FRL mode, each channel can operate at 6 Gbps, 8 Gbps, 10 Gbps, or 12 Gbps.

FRL mode uses Category 3 (Cat 3) cable to ensure good signal integrity.

HDMI data stream

The HDMI data stream contains two types.

1- Data for transferring colors

A packed representation of the video pixels timed with the source pixel clock.

Encoded using the TMDS 8b/10b algorithm.

2- Data for transmitting auxiliary

Transmits audio data along with a series of auxiliary packets.

The receiving device uses the auxiliary packets to properly reconstruct the video and audio data.

Encoded using the TMDS Error Reduction Coding - 4-bit (TERC4) encoding algorithm.

Each data stream section is preceded with guard bands and pre-ambles. The guard bands and pre-ambles allow for accurate synchronization with received data streams.

The following figures show the arrangement of video data, video data enable, video H-SYNC and video V-SYNC in 1, 2, 4 and 8 pixels per clock.

  • ● Video Data, Video Data Valid, H-SYNC, and V-SYNC—1 Pixel per Clock

3_HDMI-One-Pixel-per-Clock

  • ● Video Data, Video Data Valid, H-SYNC, and V-SYNC—2 Pixels per Clock

4_HDMI-Two-Pixels-per-Clock

  • ● Video Data, Video Data Valid, H-SYNC, and V-SYNC—4 Pixels per Clock

5_HDMI-Four-Pixels-per-Clock

  • ● Video Data, Video Data Valid, H-SYNC, and V-SYNC—8 Pixels per Clock

6_HDMI-Eight-Pixels-per-Clock



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By HornmicLink_Henry @221213 17:53