Mon Jun 19 21:07:00 CST 2023
PCI-Express (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard, which was originally named "3GIO" and was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards. PCI, PCI-X and AGP bus standards. pci or pcie interface is very common in pc machines, graphics cards, network cards, sound cards are connected to the cpu through the pci or in the pcie interface.
PCIe expansion slots on PCs are usually available in x1, x4, x8, and x16. These numbers indicate how many "lanes" each expansion slot has. The more lanes a slot has, the faster the data flow to and from the card. For example, modern graphics cards use x16 slots, while M.2 "gum stick" NVMe SSDs use special slots with two or four lanes.
PCIe is also backwards compatible. If you have a PCIe 4.0 card, you can use it with a motherboard designed for PCIe 3.0; but then, the bandwidth available on this card will be limited to the capabilities of PCIe 3.0. A PCIe 3.0 card can fit into a PCIe 4.0 slot, but it will again be limited by PCIe 3.0.
PCI-SIG, the standards committee behind the PCIe interface standard, announced that the PCIe 7.0 specification is targeted for release to its members in 2025 at data rates up to 128 GT/s. This translates to 512 GB/s of bi-directional throughput over a 16-channel (x16) connection, before encoding overhead. PCI-SIG is the consortium behind the PCIe interface, an open industry standard comprised of more than 900 member companies.
PCI-SIG notes that the PCIe 7.0 interface will provide up to 512 GB/s of bi-directional throughput over x16 connections, but this is before the impact of encoding overhead and header efficiency, both of which affect available bandwidth.
The PCIe 7.0 interface will continue to use 1b/1b flit mode encoding and the PAM4 signaling technology introduced with PCIe 6.0, which is a significant improvement over the 128b/130b encoding and NRZ signaling used in the PCIe 3.0 through PCIe 5.0 specifications. As a result, the actual available bandwidth will be slightly less than the 512 GB/s figure, but still represents twice the PCIe 6.0 interface.
As we saw in the jump to PCIe 4.0 and 5.0, the length of PCIe alignments will again be reduced due to faster signal rates. This means that the minimum allowable distance between the PCIe root device (e.g. CPU) and the end device (e.g. GPU) will be shorter without additional components.
The groundwork for the PCIe 7.0 specification follows the PCI-SIG's completion of the PCIe 6.0 specification earlier this year, which will provide double the bandwidth of the previous generation PCIe 6.0 interface.
But you won't see PCIe 7.0 devices on the market for quite some time, although PCI-SIG is now beginning to define the specification and hopes to meet its goal of releasing a new specification every three years. the PCIe 7.0 specification is expected to land in 2025, but we won't see end devices until 2028.
-Provides 128 GT/s raw bit rate and up to 512 GB/s bi-directional transmission rate via x16 configuration
-Utilizes PAM4 (Pulsed Amplitude Modulation at 4 levels) signaling
-Focuses on channel parameters and coverage
-Continues to deliver low latency and high reliability goals
-Improves power efficiency
-Maintains backward compatibility with all previous generations of PCIe technology
-Symbol List
PCI-SIG doubles the bandwidth of the PCIe specification every three years to meet the challenges of emerging applications and markets. Today's announcement of PCI-SIG's plan to double channel speeds to 512 GB/s (bi-directional) puts it on track to double PCIe specification performance in another 3-year cycle.
The PCIe 7.0 specification is designed to support emerging applications such as 800 G Ethernet, AI/ML, cloud and quantum computing, data-intensive markets such as hyperscale data centers, high-performance computing (HPC), and military/aerospace.
PCIe Layer Segmentation
The hierarchical structure of the PCIe bus is similar to that of a network, but each layer of the PCIe bus is implemented using hardware logic. In the PCIe architecture, data messages are first generated in the Device Core layer and then sent out through the Transaction Layer, Data Link Layer and Physical Layer of the device. The data at the receiving end also needs to pass through the Physical Layer, Data Link Layer and Transaction Layer, and finally reaches the Device Core.
By HornmicLink_Henry @230619 21:08